Union, Struct and Defined Data Types

QN8066 data representation. More...

Classes
union	qn8066_system1
	System1 - Sets device modes (Address: 00h) More...
union	qn8066_system2
	System2 - Sets device modes (Address: 01h) More...
union	qn8066_cca
	CCA - Sets CCA parameters ( Address: 02h) More...
union	qn8066_snr
	SRN - Estimate RF input CNR value( Address: 03h - Read Only) More...
union	qn8066_rssisig
	RSSISIG - In-band signal RSSI (Received signal strength indicator) dBuV value. dBuV=RSSI-49( Address: 04h - Read Only) More...
union	qn8066_cid1
	CID1 - Device ID numbers ( Address: 05h - Read Only) More...
union	qn8066_cid2
	CID2 - Device ID numbers ( Address: 06h - Read Only) More...
union	qn8066_xtal_div0
	XTAL_DIV0 - Frequency select of reference clock source (Lower bits - Address: 07h - Write Only) More...
union	qn8066_xtal_div1
	XTAL_DIV1 - Frequency select of reference clock source (Lower bits - Address: 08h - Write Only) More...
union	qn8066_xtal_div2
	XTAL_DIV2 - Frequency select of reference clock source (Lower bits - Address: 09h - Write Only) More...
union	qn8066_status1
	STATUS1 - System status ( Address: 0Ah - Read Only) More...
union	qn8066_rx_ch
	RX_CH - Lower 8 bit of 10-bit receiver channel index (Address: 0Bh - Write Only) More...
union	qn8066_ch_start
	CH_START - Lower 8 bits of 10-bit CCA(channel scan) start channel index (Address: 0Ch - Write Only) More...
union	qn8066_ch_stop
	CH_STOP - Lower 8 bits of 10-bit channel scan stop channel index (Address: 0Dh - Write Only) More...
union	qn8066_ch_step
	CH_STEP - Channel scan frequency step (Address: 0Eh - Write Only) More...
union	qn8066_rx_rds
	RDS - RDS data byte 0 to byte 7 (Address: 0Fh to 16h - Read Only) More...
union	qn8066_status2
	STATUS2 - Receiver RDS status indicators (Address: 17h - Read Only) More...
union	qn8066_vol_ctl
	VOL_CT - Audio volume control (Address: 18h - Write Only) More...
union	qn8066_int_ctrl
	INT_CTRL - Receiver RDS control (Address: 19h - Write Only) More...
union	qn8066_status3
	STATUS3 - Receiver audio peak level and AGC status (Address: 1Ah - Read Only) More...
union	qn8066_txch
	TXCH - Lower 8 bit of 10-bit transmitter channel index (Address: 1Bh - Read and Write) More...
union	qn8066_tx_rds
	RDS - RDS tx data from byte 0 to byte 7 (Address: 1Ch to 23h - Write Only) More...
union	qn8066_pac
	PAC - PA output power target control (Address: 24h - Write Only) More...
union	qn8066_fdev
	FDEV - Specify total TX frequency deviation (Address: 25h - Write Only) More...
union	qn8066_rds
	RDS - Specify transmit RDS frequency deviation (Address: 26h - Write Only) More...
union	qn8066_gplt
	GPLT - Transmitter soft chip threshold, gain of TX pilot (Address: 27h. More...
union	qn8066_reg_vga
	REG_VGA - X AGC gain (Address: 28h - Read and Write) More...
union	RDS_BLOCK1
	RDS - First block (RDS_BLOCK1 datatype) More...
union	RDS_BLOCK2
	Block 2 (RDS_BLOCK2 data type) More...
union	RDS_BLOCK3
	Block 3 (RDS_BLOCK3 data type) More...
union	RDS_BLOCK4
	Block 4 (RDS_BLOCK4 data type) More...
struct	qn8066_system1.arg
struct	qn8066_system2.arg
struct	qn8066_cca.arg
struct	qn8066_cid1.arg
struct	qn8066_cid2.arg
struct	qn8066_xtal_div1.arg
struct	qn8066_status1.arg
struct	qn8066_ch_step.arg
struct	qn8066_rx_rds.arg
struct	qn8066_status2.arg
struct	qn8066_vol_ctl.arg
struct	qn8066_int_ctrl.arg
struct	qn8066_status3.arg
struct	qn8066_tx_rds.arg
struct	qn8066_pac.arg
struct	qn8066_rds.arg
struct	qn8066_gplt.arg
struct	qn8066_reg_vga.arg
struct	RDS_BLOCK1.field
struct	RDS_BLOCK2.commonFields
struct	RDS_BLOCK2.group0Field
struct	RDS_BLOCK2.group2Field
struct	RDS_BLOCK4.utc

Detailed Description

QN8066 data representation.

Data Types

---

Class Documentation

qn8066_system1

union qn8066_system1

System1 - Sets device modes (Address: 00h)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 19

Class Members
struct qn8066_system1.arg	arg
uint8_t	raw

qn8066_system2

union qn8066_system2

System2 - Sets device modes (Address: 01h)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 20

Class Members
struct qn8066_system2.arg	arg
uint8_t	raw

qn8066_cca

union qn8066_cca

CCA - Sets CCA parameters ( Address: 02h)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 21

Class Members
struct qn8066_cca.arg	arg
uint8_t	raw

qn8066_snr

union qn8066_snr

SRN - Estimate RF input CNR value( Address: 03h - Read Only)

Estimated RF input SNR.

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 21

Class Members
uint8_t	SNRDB
uint8_t	raw

qn8066_rssisig

union qn8066_rssisig

RSSISIG - In-band signal RSSI (Received signal strength indicator) dBuV value. dBuV=RSSI-49( Address: 04h - Read Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 22

Class Members
uint8_t	RSSISIG
uint8_t	raw

qn8066_cid1

union qn8066_cid1

CID1 - Device ID numbers ( Address: 05h - Read Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 22

Class Members
struct qn8066_cid1.arg	arg
uint8_t	raw

qn8066_cid2

union qn8066_cid2

CID2 - Device ID numbers ( Address: 06h - Read Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 22

Class Members
struct qn8066_cid2.arg	arg
uint8_t	raw

qn8066_xtal_div0

union qn8066_xtal_div0

XTAL_DIV0 - Frequency select of reference clock source (Lower bits - Address: 07h - Write Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 23

Class Members
uint8_t	xtal_div
uint8_t	raw

qn8066_xtal_div1

union qn8066_xtal_div1

XTAL_DIV1 - Frequency select of reference clock source (Lower bits - Address: 08h - Write Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 23

Class Members
struct qn8066_xtal_div1.arg	arg
uint8_t	raw

qn8066_xtal_div2

union qn8066_xtal_div2

XTAL_DIV2 - Frequency select of reference clock source (Lower bits - Address: 09h - Write Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 23

Class Members
uint8_t	pll_dlt
uint8_t	raw

qn8066_status1

union qn8066_status1

STATUS1 - System status ( Address: 0Ah - Read Only)

FSM Status	Description
0 - 0000	STBY
1 - 0001	RESET
2 - 0010	CALI
3 - 0011	IDLE
4 - 0100	CALIPLL
5 - 0101	Reserved
6 - 0110	Reserved
7 - 0111	TXPLLC
8 - 1000	TX_RSTB
9 - 1001	PACAL
10 - 1010	TRANSMIT
11 - 1011	TXCCA
Others	Reserved

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 24

Class Members
struct qn8066_status1.arg	arg
uint8_t	raw

qn8066_rx_ch

union qn8066_rx_ch

RX_CH - Lower 8 bit of 10-bit receiver channel index (Address: 0Bh - Write Only)

Channel used for RX have two origins, one is from RXCH register (REG0EH[1:0]+REG0BH)

which can be written by the user, another is from CCA. CCA selected channel is stored in an internal register, which is

physically a different register with CH register, but it can be read out through register CH and be used for RX when

CCA_CH_DIS(REG0[0])=0.

FM channel: (60+RXCH*0.05)MHz

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 25

Class Members
uint8_t	RXCH
uint8_t	raw

qn8066_ch_start

union qn8066_ch_start

CH_START - Lower 8 bits of 10-bit CCA(channel scan) start channel index (Address: 0Ch - Write Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 25

Class Members
uint8_t	CH_START
uint8_t	raw

qn8066_ch_stop

union qn8066_ch_stop

CH_STOP - Lower 8 bits of 10-bit channel scan stop channel index (Address: 0Dh - Write Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 25

Class Members
uint8_t	CH_STOP
uint8_t	raw

qn8066_ch_step

union qn8066_ch_step

CH_STEP - Channel scan frequency step (Address: 0Eh - Write Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 26

Class Members
struct qn8066_ch_step.arg	arg
uint8_t	raw

qn8066_rx_rds

union qn8066_rx_rds

RDS - RDS data byte 0 to byte 7 (Address: 0Fh to 16h - Read Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 26-28

Class Members
struct qn8066_rx_rds.arg	arg
uint8_t	data[8]

qn8066_status2

union qn8066_status2

STATUS2 - Receiver RDS status indicators (Address: 17h - Read Only)

RDS_RXUPD - RDS RX: RDS received group updated. Each time a new group is received, this bit will be toggled.

If RDS_INT_EN=1, then at the same time this bit is toggled, interrupt output will out put a 4.5 ms low pulse

0->1 or 1->0 -> A new set (8 Byte) of data is received

0->0 or 1->1 -> New data is in receiving

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 28-29

Class Members
struct qn8066_status2.arg	arg
uint8_t	raw

qn8066_vol_ctl

union qn8066_vol_ctl

VOL_CT - Audio volume control (Address: 18h - Write Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 29

Class Members
struct qn8066_vol_ctl.arg	arg
uint8_t	raw

qn8066_int_ctrl

union qn8066_int_ctrl

INT_CTRL - Receiver RDS control (Address: 19h - Write Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 30

Class Members
struct qn8066_int_ctrl.arg	arg
uint8_t	raw

qn8066_status3

union qn8066_status3

STATUS3 - Receiver audio peak level and AGC status (Address: 1Ah - Read Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 30-31

Class Members
struct qn8066_status3.arg	arg
uint8_t	raw

qn8066_txch

union qn8066_txch

TXCH - Lower 8 bit of 10-bit transmitter channel index (Address: 1Bh - Read and Write)

Lower 8 bits of 10-bit Channel index. Channel used for TX have two origins, one is from TXCH register (REG19H[1:0]+REG1BH) which can be written by the user,

another is from CCS. CCS selected channel is stored in an internal register, which is physically a different register with TXCH register, but it can be read out through

register TXCH and be used for TX when CCS_CH_DIS(REG0[0])=0. FM channel: (60+TXCH*0.05)MHz

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 31

Class Members
uint8_t	TXCH
uint8_t	raw

qn8066_tx_rds

union qn8066_tx_rds

RDS - RDS tx data from byte 0 to byte 7 (Address: 1Ch to 23h - Write Only)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 31-33

Class Members
struct qn8066_tx_rds.arg	arg
uint8_t	data[8]

qn8066_pac

union qn8066_pac

PAC - PA output power target control (Address: 24h - Write Only)

PA_TRGT - PA output power target is 0.91*PA_TRGT+70.2dBu. Valid values are 24-56.

TXPD_CLR - TX aud_pk clear signal. Audio peak value is max-hold and stored in aud_pk[3:0]. Once TXPD_CLR is toggled, the aud_pk value is cleared and restarted again.

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 33

Class Members
struct qn8066_pac.arg	arg
uint8_t	raw

qn8066_fdev

union qn8066_fdev

FDEV - Specify total TX frequency deviation (Address: 25h - Write Only)

Specify total TX frequency deviation. TX frequency deviation = 0.69KHz*TX_FEDV. From 0 to 255

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 33

Class Members
uint8_t	TX_FDEV	Specify total TX frequency deviation. TX frequency deviation = 0.69KHz*TX_FEDV. From 0 to 255
uint8_t	raw

qn8066_rds

union qn8066_rds

RDS - Specify transmit RDS frequency deviation (Address: 26h - Write Only)

RDSFDEV - RDS frequency deviation = 0.35KHz*RDSFDEV in normal mode. RDS frequency deviation = 0.207KHz*RDSFDEV in 4k mode and private mode. Values = from 0 to 127

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 34

Class Members
struct qn8066_rds.arg	arg
uint8_t	raw

qn8066_gplt

union qn8066_gplt

GPLT - Transmitter soft chip threshold, gain of TX pilot (Address: 27h.

• Write Only)

GAIN_TXPLT	value
7 - 0111	7% * 75KHz
8 - 1000	8% * 75KHz
9 - 1001	9% * 75KHz
10 - 1010	10% * 75KHz

t1m_sel	value
0 - 00	57s
1 - 01	58s
2 - 10	59s
3 - 11	Infinity (Never)

tx_sftclpth	value
0 - 00	12’d2051 (3db back off from 0.5v)
1 - 01	12’d1725 (4.5db back off from 0.5v)
2 - 10	12’d1452 (6db back off from 0.5v)
3 - 11	12’d1028 (9db back off from 0.5v)

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 34

Class Members
struct qn8066_gplt.arg	arg
uint8_t	raw

qn8066_reg_vga

union qn8066_reg_vga

REG_VGA - X AGC gain (Address: 28h - Read and Write)

Attenuation/Gain depending on RIN - 0, 1, 2 AND 3 RESPECTIVELY. See tables below.

RIN	Input impedance (K Ohoms)
0 - 00	10
1 - 01	20
2 - 10	40
3 - 11	80

TXAGC_GDB	TX digital gain
0 - 00	0 dB
1 - 01	1 dB
2 - 10	2 dB
3 - 11	Reserved

TXAGC_GVGA	Attenuation/Gain depending on RIN - 0, 1, 2 AND 3 RESPECTIVELY
0 - 000	3; -3; -9; -15
1 - 001	6; 0; -6; -12
2 - 010	9; 3; -3; -9
3 - 011	12; 6; 0; -6
4 - 100	15; 9; 3; -3
5 - 101	18; 12; 6; 0
Others	Reserved

See also

Data Sheet - Quintic - QN8066 - Digital FM Transceiver for Portable Devices, pag. 35

Class Members
struct qn8066_reg_vga.arg	arg
uint8_t	raw

RDS_BLOCK1

union RDS_BLOCK1

RDS - First block (RDS_BLOCK1 datatype)

PI Code Function: Identifies the radio station. This code is essential

for allowing receivers to identify the source of the radio signal.

Class Members
struct RDS_BLOCK1.field	field
unsigned char	byteContent[2]
uint16_t	pi

RDS_BLOCK2

union RDS_BLOCK2

Block 2 (RDS_BLOCK2 data type)

Specifies the type of data being transmitted and includes information such as

program type (e.g., news, music) and whether the station transmits traffic information.

The table below show some program types you can use to check your transmitter.

PTY Code	Program Type
0	No PTY (undefined)
1	News
3	Information
4	Sport
5	Education
7	Culture
8	Science
10	Pop Music
11	Rock Music
15	Other Music
16	Weather
17	Finance
18	Children's Programs
20	Religion
24	Jazz Music
25	Country Music
26	National Music
27	Oldies Music
28	Folk Music
29	Documentary
31	Alarm

For GCC on System-V ABI on 386-compatible (32-bit processors), the following stands: 1) Bit-fields are allocated from right to left (least to most significant). 2) A bit-field must entirely reside in a storage unit appropriate for its declared type. Thus a bit-field never crosses its unit boundary. 3) Bit-fields may share a storage unit with other struct/union members, including members that are not bit-fields. Of course, struct members occupy different parts of the storage unit. 4) Unnamed bit-fields' types do not affect the alignment of a structure or union, although individual bit-fields' member offsets obey the alignment constraints.

See also

also https://en.wikipedia.org/wiki/Radio_Data_System

Class Members
struct RDS_BLOCK2.commonFields	commonFields
struct RDS_BLOCK2.group0Field	group0Field
struct RDS_BLOCK2.group2Field	group2Field
unsigned char	byteContent[2]
uint16_t	raw	Raw 16-bit representation.

RDS_BLOCK3

union RDS_BLOCK3

Block 3 (RDS_BLOCK3 data type)

Class Members
unsigned char	byteContent[2]
uint16_t	raw

RDS_BLOCK4

union RDS_BLOCK4

Block 4 (RDS_BLOCK4 data type)

Class Members
unsigned char	byteContent[2]
struct RDS_BLOCK4.utc	utc
uint16_t	raw

qn8066_system1.arg

struct qn8066_system1.arg

Class Members
uint8_t	cca_ch_dis: 1	0 = RX_CH is decided by internal CCA; 1 = RX_CH is decided writing in RX_CH[9:0]
uint8_t	ccs_ch_dis: 1	0 = TX_CH is decided by internal CCS; 1 = TX_CH is decided writing in TX_CH[9:0]
uint8_t	chsc: 1	Channel Scan mode enable - 0 = Normal operation; 1 = Channel Scan mode operation.
uint8_t	txreq: 1	Transmission request - 0 = Non TX mode; 1 = Enter transmit mode.
uint8_t	rxreq: 1	Receiving request - 0 = Non RX mode; 1 = Enter Receiving mode.
uint8_t	stnby: 1	Request Immediately enter Standby mode whatever state chip is in - 0 = Non standby mode; 1 = Enter standby mode.
uint8_t	recal: 1	Reset the state to initial states and recalibrate all blocks - 0 = No action. FSM runs normally; 1 = Reset the FSM. After this bit is de-asserted, FSM will go through all the power up and calibration sequence.
uint8_t	swrst: 1	Reset all registers to default values; 0 = Keep the current value; 1 = Reset to default values.

qn8066_system2.arg

struct qn8066_system2.arg

Class Members
uint8_t	tc: 1	Pre-emphasis and de-emphasis time constant; 0 = 50; 1 = 75.
uint8_t	rdsrdy: 1	RDS transmitting ready; - If user want the chip transmitting all the 8 bytes in RDS0~RDS7, user should toggle this bit.
uint8_t	tx_mute: 1	TX audio mute enabel - 0 = Mute Disabled; 1 = Mute Enabled;.
uint8_t	rx_mute: 1	RX audio Mute enable - 0 = Mute Disabled; 1 = Mute Enabled.
uint8_t	tx_mono: 1	TX stereo and mono mode selection; 0 = Stereo; 1 = Mono.
uint8_t	force_mo: 1	Force receiver in MONO mode; 0 = Not forced. ST/MONO auto selected; Forced in MONO mode.
uint8_t	tx_rdsen: 1	Transmitter RDS enable; 0 = RDS Disable; 1 = RDS Enable.
uint8_t	rx_rdsen: 1	Receiver RDS enable; 0 = RDS Disable; 1 = RDS Enable.

qn8066_cca.arg

struct qn8066_cca.arg

Class Members
uint8_t	SNR_CCA_TH: 6	The threshold for determination of whether current channel is valid by check its SNR.
uint8_t	imr: 1	Image Rejection. 0 = LO<RF, image is in lower side; 1 = LO>RF, image is in upper side.
uint8_t	xtal_inj: 1	Select the reference clock source. 0 = Inject sine-wave clock; 1 = Inject digital clock.

qn8066_cid1.arg

struct qn8066_cid1.arg

Class Members
uint8_t	CID2: 2	Chip ID for minor revision: 1~4.
uint8_t	CID1: 3	Chip ID for product family: 000 = FM; others Reserved.
uint8_t	RSVD: 3	Reserved.

qn8066_cid2.arg

struct qn8066_cid2.arg

Class Members
uint8_t	CID4: 2	Sequency integer values from 0 to 4.
uint8_t	CID3: 6	Chip ID for product ID. 001101 = Transceiver – QN8066; Others = Reserved unkown.

qn8066_xtal_div1.arg

struct qn8066_xtal_div1.arg

Class Members
uint8_t	xtal_div: 3	Higher 3 bits of xtal_div[10:0]. Xtal_div[10:0] = round(freq of xtal/32.768KHz)
uint8_t	pll_dlt: 5	Lower 5 bits of pll_dlt[12:0].

qn8066_status1.arg

struct qn8066_status1.arg

Class Members
uint8_t	ST_MO_RX: 1	< Stereo receiving status. 0 = Stereo; 1 = Mono
uint8_t	RXSTATUS: 1	< RX Status. 0 = No receiving; 1 = Receiving
uint8_t	RXAGCSET: 1	< RX AGC Settling status. 0 = Not settled; 1 = Settled
uint8_t	rxcca_fail: 1	< RXCCA status flag. To indicate whether a valid channel is found during RX CCA. 0 = RX CCA success to find a valid channel; 1 = RX CCA fail to find a valid channel
uint8_t	FSM: 4	< Top FSM state code

qn8066_ch_step.arg

struct qn8066_ch_step.arg

Class Members
uint8_t	RXCH: 2	Highest 2 bits of 10-bit channel index. Channel freq is (60+RXCH*0.05)MHz.
uint8_t	CH_STA: 2	Highest 2 bits of 10-bit CCA(channel scan) start channel index. Start freq is (60+RXCH_STA*0.05)MHz.
uint8_t	CH_STP: 2	Highest 2 bits of 10-bit CCA(channel scan) stop channel index. Stop freq is (60+RXCH_STP*0.05)MHz.
uint8_t	CH_FSTEP: 2	CCA (channel scan) frequency step. 00=50kHz; 01=100kHz; 10 = 200kHz; 11=Reserved.

qn8066_rx_rds.arg

struct qn8066_rx_rds.arg

Class Members
uint8_t	RX_RDSD0	RDS data byte 0 - 0Fh.
uint8_t	RX_RDSD1	RDS data byte 1 - 10h.
uint8_t	RX_RDSD2	RDS data byte 2 - 11h.
uint8_t	RX_RDSD3	RDS data byte 3 - 12h.
uint8_t	RX_RDSD4	RDS data byte 4 - 13h.
uint8_t	RX_RDSD5	RDS data byte 5 - 14h.
uint8_t	RX_RDSD6	RDS data byte 6 - 15h.
uint8_t	RX_RDSD7	RDS data byte 7 - 16h.

qn8066_status2.arg

struct qn8066_status2.arg

Class Members
uint8_t	RDS3ERR: 1	0 = No Error
uint8_t	RDS2ERR: 1	0 = No Error
uint8_t	RDS1ERR: 1	0 = No Error
uint8_t	RDS0ERR: 1	0 = No Error
uint8_t	RDSSYNC: 1	RDS block synchronous indicator. 0 = Non-synchronous; 1 = Synchronous.
uint8_t	RDSC0C1: 1	Type indicator of the RDS third block in one group. 0 = C0; 1 = C1.
uint8_t	E_DET: 1	‘E’ block (MMBS block) detected. 0 = Not detected; 1 = Detected
uint8_t	RDS_RXUPD: 1	RDS received group updated. Each time a new group is received, this bit will be toggled. See comment above.

qn8066_vol_ctl.arg

struct qn8066_vol_ctl.arg

Class Members
uint8_t	GAIN_ANA: 3	set volume control gain of analog portion. From 0 to 7
uint8_t	GAIN_DIG: 3	set digital volume gain. From 0 to 5
uint8_t	DAC_HOLD: 1	DAC output control. 0 = Normal operation; 1 = Hold DAC output to a fixed voltage.
uint8_t	TX_DIFF: 1	Tx audio input mode selection. 0 = Single ended; 1 = Differential.

qn8066_int_ctrl.arg

struct qn8066_int_ctrl.arg

Class Members
uint8_t	TXCH: 2	Highest 2 bits of 10-bit channel index. hannel freq is (60+TXCH*0.05)MHz
uint8_t	priv_mode: 1	Private mode for RX/TX.
uint8_t	rds_4k_mode: 1	Enable RDS RX/TX 4k Mode: with or without the privacy mode (audio scramble and RDS encryption)
uint8_t	s1k_en: 1	Internal 1K tone selection. It will be used as DAC output when RXREQ. 0 = Disabled; 1 = Enabled
uint8_t	rds_only: 1	RDS Mode Selection. 0 = Received bit-stream have both RDS and MMBS blocks (‘E’ block); 1 = Received bit-stream has RDS block only, no MMBS block (‘E’ block)
uint8_t	cca_int_en: 1	RX CCA interrupt enable. When CCA_INT_EN=1, a 4.5ms low pulse will be output from pad din (RX mode) when a RXCCA (RX mode) is finished. 0 = Disabled; 1 = Enabled
uint8_t	rds_int_en: 1	RDS RX interrupt enable. When RDS_INT_EN=1, a 4.5ms low pulse will be output from pad din (RX mode) when a new group data is received and stored into RDS0~RDS7 (RX mode). 0 = Disabled; 1 = Enabled

qn8066_status3.arg

struct qn8066_status3.arg

Class Members
uint8_t	rsvd: 1	Reserved.
uint8_t	rxagcerr: 1	RXAGC Error Flag. 0 = No Error; 1 = Error.
uint8_t	RDS_TXUPD: 1	RDS TX: To transmit the 8 bytes in RDS0~RDS7, user should toggle the register bit RDSRDY. Then the chip internally fetches these bytes after completing transmitting of current group. Once the chip internally fetched these bytes, it will toggle this bit, and user can write in another group.
uint8_t	aud_pk: 4	Audio peak value at ADC input is aud_pk * 45mV.
uint8_t	CAP_SH: 1	Large CAP short detection flag. 1 indicates a short. This bit is the OR-ed result of Poly phase filter I path and Poly phase filter Q path.

qn8066_tx_rds.arg

struct qn8066_tx_rds.arg

Class Members
uint8_t	TX_RDSD0	RDS data byte 0 - 0Fh.
uint8_t	TX_RDSD1	RDS data byte 1 - 10h.
uint8_t	TX_RDSD2	RDS data byte 2 - 11h.
uint8_t	TX_RDSD3	RDS data byte 3 - 12h.
uint8_t	TX_RDSD4	RDS data byte 4 - 13h.
uint8_t	TX_RDSD5	RDS data byte 5 - 14h.
uint8_t	TX_RDSD6	RDS data byte 6 - 15h.
uint8_t	TX_RDSD7	RDS data byte 7 - 16h.

qn8066_pac.arg

struct qn8066_pac.arg

Class Members
uint8_t	PA_TRGT: 7	PA output power target is 0.91*PA_TRGT+70.2dBu. Valid values are 24-56.
uint8_t	TXPD_CLR: 1	TX aud_pk clear signal. Audio peak value is max-hold and stored in aud_pk[3:0]. Once TXPD_CLR is toggled, the aud_pk value is cleared and restarted again.

qn8066_rds.arg

struct qn8066_rds.arg

Class Members
uint8_t	RDSFDEV: 7	RDS frequency deviation = 0.35KHz*RDSFDEV in normal mode. RDS frequency deviation = 0.207KHz*RDSFDEV in 4k mode and private mode. Values = from 0 to 127.
uint8_t	line_in_en: 1	Audio Line-in enable control. 0 = Disable; 1 = Enable.

qn8066_gplt.arg

struct qn8066_gplt.arg

Class Members
uint8_t	GAIN_TXPLT: 4	Gain of TX pilot to adjust pilot frequency deviation. Refer to peak frequency deviation of MPX signal when audio input is full scale.
uint8_t	t1m_sel: 2	Selection of 1 minute time for PA off when no audio.
uint8_t	tx_sftclpth: 2	TX soft clip threshold.

qn8066_reg_vga.arg

struct qn8066_reg_vga.arg

Class Members
uint8_t	RIN: 2	TX mode input impedance for both L/R channels. See table above
uint8_t	TXAGC_GDB: 2	TX digital gain. See table above.
uint8_t	TXAGC_GVGA: 3	TX input buffer gain. See table above.
uint8_t	tx_sftclpen: 1	TX soft clipping enable.

RDS_BLOCK1.field

struct RDS_BLOCK1.field

Class Members
uint8_t	reference: 7
uint8_t	programId: 4
uint8_t	countryId: 4

RDS_BLOCK2.commonFields

struct RDS_BLOCK2.commonFields

Class Members
uint16_t	additionalData: 4	Additional data bits, depending on the group.
uint16_t	textABFlag: 1	Do something if it chanhes from binary "0" to binary "1" or vice-versa.
uint16_t	programType: 5	PTY (Program Type) code.
uint16_t	trafficProgramCode: 1	(TP) => 0 = No Traffic Alerts; 1 = Station gives Traffic Alerts
uint16_t	versionCode: 1	(B0) => 0=A; 1=B
uint16_t	groupType: 4	Group Type code.

RDS_BLOCK2.group0Field

struct RDS_BLOCK2.group0Field

Class Members
uint16_t	address: 2	Depends on Group Type and Version codes. If 0A or 0B it is the Text Segment Address.
uint16_t	DI: 1	Decoder Control bit.
uint16_t	MS: 1	Music/Speech.
uint16_t	TA: 1	Traffic Announcement.
uint16_t	programType: 5	PTY (Program Type) code.
uint16_t	trafficProgramCode: 1	(TP) => 0 = No Traffic Alerts; 1 = Station gives Traffic Alerts
uint16_t	versionCode: 1	(B0) => 0=A; 1=B
uint16_t	groupType: 4	Group Type code.

RDS_BLOCK2.group2Field

struct RDS_BLOCK2.group2Field

Class Members
uint16_t	address: 4	Depends on Group Type and Version codes. If 2A or 2B it is the Text Segment Address.
uint16_t	textABFlag: 1	Do something if it changes from binary "0" to binary "1" or vice-versa.
uint16_t	programType: 5	PTY (Program Type) code.
uint16_t	trafficProgramCode: 1	(TP) => 0 = No Traffic Alerts; 1 = Station gives Traffic Alerts
uint16_t	versionCode: 1	(B0) => 0=A; 1=B
uint16_t	groupType: 4	Group Type code.

RDS_BLOCK4.utc

struct RDS_BLOCK4.utc

Class Members
uint16_t	offset: 5	Local Time Offset
uint16_t	offset_sign: 1	Offset sign (+/-)
uint16_t	min: 6	UTC Minutes (0–59)
uint16_t	hour: 4	Four least significant bits of the hour - UTC Hours (0–23)